The present invention relates to an analog equalization circuit for amplified signals originating from a transducer and, more particularly, to a low pass filter architecture with programmable equalization characteristics.
In analog or digital data read/acquisition systems using transducers, after pre-amplifying the signal and eventually implementing automatic gain regulation, it is almost unavoidable to effect an equalization. This includes increasing the gain in the range of the frequency spectrum where the signal generated by a transducer has the maximum energy. The read channels of data recorded on mass memory devices, such as, for example, typical hard disk drives (HDDs), require similar processing including an analog pre-equalization which increases the read channel gain in the frequency range where the signals have the maximum energy.
Typically, the read channels perform this analog pre-equalization operation, or in any case a first part of it, by modifying the frequency response profile of a low pass filter, i.e. introducing two real and opposite zeros in transfer function. In this way, the group-delay parameter (that is the phase delay df, where f is the phase of transfer function) remains unchanged.
FIG. 1 shows the conventional structure of a biquadratic cell (BIQUAD), whose transfer function vo/vi, in the domain of the variable s (Laplace transform), is given by:       vo    vi    =                    gm        Q1            /              gm        Q4                    1      +              s        *        C1        *                              gm            Q3                    /                      (                                          gm                Q2                            *                              gm                Q4                                      )                              +                        s          2                *        C1        *                  C2          /                      (                                          gm                Q2                            *                              gm                Q4                                      )                              
To simplify description, all illustrations are of a single-ended architecture, employing a bipolar transconductor device. However, as it will be evident to any skilled person, all circuits shown and described according to a single-ended embodiment may be realized also in a fully differential embodiment and may employ a transconductor of any type, for example made in CMOS technology instead of in a bipolar junction technology.
As highlighted in the scheme of FIG. 1, the two programmable real and opposed zeros are implemented by injecting on the output node of the circuit of FIG. 1, a current given by:
iz=k*s*Cz*Vi
where k is the current gain of the buffer stage of the injection current iz, such to obtain the conventional circuit used in the read channels, shown in FIG. 2.
As is well known to the skilled artisan, the problem with the known circuit of FIG. 2 is to assure that the parasitic pole gmQ5/Cz remains securely positioned at a frequency higher than that of the other poles of the transfer function, to obtain a transfer function which, in first approximation (that is by neglecting the parasitic pole gmQ5/Cz if sufficiently far from the filter""s band), is given by:       vo    vi    =                              gm          Q1                /                  gm          Q4                    -                        s          2                *                  C3          /          C2                *        C1        *                  C2          /                      (                                          gm                Q2                            *                              gm                Q4                                      )                                      1      +              s        *        C1        *                              gm            Q3                    /                      (                                          gm                Q2                            *                              gm                Q4                                      )                              +                        s          2                *        C1        *                  C2          /                      (                                          gm                Q2                            *                              gm                Q4                                      )                              
This requirement implies a non-negligible power consumption for ensuring the above indicated condition. For the known circuit of FIG. 2, this condition may be expressed by the following inequality:
gmQ5/CZ greater than  greater than sqrt(gmQ2*gMQ4/(C1*C2)
On the other hand, for noise immunity and matching reasons, Cz must be approximately equal to C1 and C2 and therefore gmQ5 must be much greater than gmQ2 and gMQ4. By considering that the power absorbed is directly proportional to the transconductance gm of the stage, the commonly used equalization circuits, as illustrated in FIG. 2, imply a high power dissipation.
In view of the state of the art, a way to avoid such a power dissipation for keeping the parasitic poles of the transfer function of the circuit that generates two programmable real and opposed zeroes, at a frequency sufficiently higher than the frequency spectrum of the transducer signal is now provided.
This important result is obtained, according to the present invention, by providing a low pass function has two distinct and real poles, formed by two structurally similar circuits and functionally connected in cascade to one another. Each circuit comprises a biquadratic cell and an input stage having a current output and a voltage output. In order to introduce two real and opposed zeroes in the filter""s transfer function, in each of the two circuits in cascade, the current output of the input stage is coupled to the node of the input capacitor of the respective biquadratic cell, directly in the first circuit and in an inverted manner in the second circuit. The voltage output of the input stage is coupled to the input of the respective biquadratic cell.
In the case of a single-ended low pass filter, the inversion of the current proportional to the derivative of the relative input voltage may be provided by a current inverting stage. In the case of a fully differential low pass filter, the necessary inversion of the injected current may be simply provided by crossing the relative connections, without the need for a current inverting stage.